The present disclosure relates, generally, to liquid crystal displays and active-matrix organic light emitting diode displays and, more particularly, to a variation-tolerant, self-repairing design methodology that may be used to compensate for variations in the low temperature polycrystalline silicon thin film transistors used in such displays.
In response to the rapid growth of demand for low power, high resolution, and low cost electronic displays, various advanced displays have been developed. Examples include three-dimensional (3D) displays for more attractive and exciting viewing experiences, memory-integrated displays for extremely low power consumption, and displays with in-cell touch and photo sensors for intuitive screen operation. These and other advanced displays require either high pixel density or multiple transistors in each pixel, leading to a small aperture ratio. This small aperture ratio, however, greatly increases the total power needed to maintain the same display luminance. Consequently, the scaling of transistor size into the nanometer regime is inevitable for retaining sufficient aperture ratio.
Low temperature polycrystalline silicon (LTPS) thin film transistors (TFTs) are promising devices for the backplane electronics of high-performance liquid crystal displays (LCDs) and active-matrix organic light emitting diode (AMOLED) displays, due to their higher driving capability, lower operating voltage, and better reliability than the amorphous silicon TFT. However, LTPS TFTs suffer from a diverse and complicated grain distribution, and a spread in the electrical characteristics of individual LTPS TFTs (e.g., threshold voltage, mobility, etcetera) is unavoidable. This often results in high leakage and low drivability transistors in a portion of pixels and, hence, causes non-uniformity of brightness over the display area. In addition, the spread of device characteristics deteriorates with device scaling, especially when the grain size is close to the device dimension. Such severe device variations not only limit the application of LTPS technology in large-sized displays but also inhibit TFT scaling for low power, high pixel density, and high integration.
Conventionally, the peripheral and control circuits of an LTPS-based display use bulk silicon and are integrated externally. As a result, the peripheral and control circuits are less susceptible to variations, as compared to the LTPS pixel array. Minimizing the variation in pixel switches is important for robust panel design. Several techniques for decreasing the variation of leakage current in pixel switches have been proposed. Mitigating the electric field near the drain region, using a lightly doped drain (LDD), and employing a dual-gate structure can effectively reduce the leakage current induced by the field emission via trap states. Techniques for suppressing the variation in drivability of pixel switches, however, have been rarely discussed. To ensure sufficient drivability in all pixel switches, increasing the supply voltage to account for the worst-case combination of variables is the most commonly applied technique. High supply voltage greatly increases power consumption and worsens the reliability of TFTs. Moreover, as the panel size or resolution is increased, yield loss—due to grain boundaries (GBs) and global variation—becomes more and more significant, even with a high supply voltage. These drawbacks have impeded the wide deployment of LTPS-based display technologies.